Method for making thin film semiconductor Hiroshi Tayanaka Abstract Read this patent Download PDF View patent at USPTO Abstract | Drawing | Description | Claims

Abstract The present invention provides new and improved methods for making crystalline semiconductor thin films which may be bonded to different kinds of substrates. The thin films may be flexible. In accordance with preferred methods, a multi-layer porous structure including two or more porous layers having different porosities is formed in a semiconductor substrate. A semiconductor thin film is grown on the porous structure. Electrodes and/or a desired support substrate may be attached to the grown film. The grown film is separated from the semiconductor substrate along a line of weakness defined in the porous structure. The separated thin film attached to the support substrate may be further processed to provide improved film products, solar panels and light emitting diode devices. These thin film semiconductors are excellent in crystallinity and may be inexpensively produced, thereby enabling production of solar cells and light emitting diodes at lower cost.

Patent number: 6194245 Filing date: Dec 7, 1999 Issue date: Feb 27, 2001 Inventor: Hiroshi Tayanaka Assignee: Sony Corporation Primary Examiner: Hsien-Ming Lee

U.S. Classification 438/57; 438/455; 438/458; 438/459

International Classification H01L 2100 Search within this patent

Citations Patent Number Title Issue date 5536361 Process for preparing semiconductor substrate by bonding to a metallic surface Jul 16, 1996 5811348 Method for separating a device-forming layer from a base body Sep 22, 1998 Referenced by Patent Number Title Issue date 6384422 Method for manufacturing semiconductor device and ultrathin semiconductor device May 7, 2002 6468824 Method for forming a semiconductor device having a metallic substrate Oct 22, 2002 6528388 Method for manufacturing semiconductor device and ultrathin semiconductor device Mar 4, 2003 6534380 Semiconductor substrate and method of manufacturing the same Mar 18, 2003 6551857 Three dimensional structure integrated circuits Apr 22, 2003 6563224 Three dimensional structure integrated circuit May 13, 2003 6602760 Method of producing a semiconductor layer on a substrate Aug 5, 2003 6632706 Three dimensional structure integrated circuit fabrication process Oct 14, 2003 6683367 Thin-film opto-electronic device and a method of making it Jan 27, 2004 6815247 Thin-film opto-electronic device and a method of making it Nov 9, 2004 7049161 Method of manufacturing substrate, method of manufacturing organic electroluminescent display device using the method, and organic electroluminescent display device May 23, 2006 7138295 Method of information processing using three dimensional integrated circuits Nov 21, 2006 7148119 Process for production of semiconductor substrate Dec 12, 2006 7157352 Method for producing ultra-thin semiconductor device Jan 2, 2007 7176545 Apparatus and methods for maskless pattern generation Feb 13, 2007 7223696 Methods for maskless lithography May 29, 2007 7242012 Lithography device for semiconductor circuit pattern generator Jul 10, 2007 Claims What is claimed is:

1. A method for making a solar cell comprising the steps of:

providing a semi-conductor substrate having a surface;
forming a porous structure adjacent the surface of the substrate including a first porous layer adjacent the surface having a first porosity, a second porous layer adjacent the first porous layer opposite the surface having a second porosity greater than said first porosity and a third porous layer in or adjacent to the second porous layer having a third porosity greater than said second porosity;
forming an epitaxially grown film semi-conductor structure on the surface including at least one hetero junction;
forming a SiO.sub.2 insulating layer on an exposed surface of the film semi-conductor structure;
patterning and etching the insulating layer to define holes;
depositing a metal film on the insulating layer to form a metal film layer;
patterning and etching the metal film layer to form electrodes disposed in the holes;
attaching elongated conductors having at least one extending end portion to the electrodes;
attaching a support substrate to the surface overlying the electrodes and conductors with a binder material; and
thereafter, separating the film semi-conductor structure and support substrate from the semi-conductor substrate along one of: a line of relative weakness defined in the third porous layer, at an interface defined between said third porous layer and the second porous layer, or adjacent an interface defined between said third porous layer and the second porous layer.

2. A method for making a solar cell as defined in claim 1, wherein the epitaxially grown film semi-conductor structure comprises a p.sup.+ /p.sup.- /n.sup.+ film semiconductor structure.

3. A method for making a solar cell as defined in claim 1 further comprising the step of applying a metal electrode to a surface of the separated film semiconductor structure opposite the support substrate.

4. A method for making a solar cell as defined in claim 1, wherein the support substrate comprises metal, glass, ceramic or polymer.

5. A method for making a solar cell as defined in claim 1, wherein the support substrate is a flexible subtrate.

6. A method for making a solar cell as defined in claim 1, wherein the support substrate and binder are transparent.

7. A method for making a semiconductor film comprising the steps of:

providing a semiconductor substrate having a surface;
forming a porous layer adjacent said surface, the porous layer comprises a first porous layer having a first porosity and a second porous layer having a second porosity higher than said first porosity and a third porous layer having a third porosity higher than said second porosity;
forming at least one semiconductor film on said surface; and
separating semiconductor film from said semiconductor substrate.

8. The method as claimed in claim 7, wherein said first porous layer is formed by anodization.

9. The method as claimed in claim 7, wherein said second porous layer is formed by anodization.

10. The method as claimed in claim 7, wherein said third porous layer is formed by anodization.

11. The method as claimed in claim 7 further comprising the step of: Only images available anandahkumar@gmail.com | My Account | Sign out Go to Google Patents Home About this patent Read this patent Thin film semiconductor and method for making thin film semiconductor Hiroshi Tayanaka Abstract Read this patent Download PDF View patent at USPTO Abstract | Drawing | Description | Claims

after said porous layer forming step and prior to said semiconductor film forming step, annealing said semiconductor substrate in a hydrogen atmosphere.

Abstract The present invention provides new and improved thin film semiconductors and methods for making crystalline semiconductor thin films which may be bonded to different kinds of substrates. The thin films may be flexible. In accordance with preferred methods, a multi-layer porous structure including two or more porous layers having different porosities is formed in a semiconductor substrate. A semiconductor thin film is grown on the porous structure. Electrodes and/or a desired support substrate may be attached to the grown film. The grown film is separated from the semiconductor substrate along a line of weakness defined in the porous structure. The separated thin film attached to the support substrate may be further processed to provide improved film products, solar panels and light emitting diode devices. These thin film semiconductors are excellent in crystallinity and may be inexpensively produced, thereby enabling production of solar cells and light emitting diodes at lower cost.

Patent number: 6326280 Filing date: Jul 14, 2000 Issue date: Dec 4, 2001 Inventor: Hiroshi Tayanaka Assignee: Sony Corporation Primary Examiner: K Christianson

U.S. Classification 438/409

International Classification H01L 2176 Search within this patent

Citations Patent Number Title Issue date 4727047 Method of producing sheets of crystalline material Feb 23, 1988 5362683 Method of making epitaxial wafers Nov 8, 1994 5811348 Method for separating a device-forming layer from a base body Sep 22, 1998 5854123 Method for producing semiconductor substrate Dec 29, 1998 5856229 Process for production of semiconductor substrate Jan 5, 1999 Referenced by Patent Number Title Issue date 6417069 Substrate processing method and manufacturing method, and anodizing apparatus Jul 9, 2002 6468841 Process for producing crystalline silicon thin film Oct 22, 2002 6649485 Method for the formation and lift-off of porous silicon layers Nov 18, 2003 6908834 Semiconductor device production method and semiconductor device Jun 21, 2005 6964732 Method and apparatus for continuous formation and lift-off of porous silicon layers Nov 15, 2005 7022585 Method for making thin film devices intended for solar cells or silicon-on-insulator (SOI) applications Apr 4, 2006 7049161 Method of manufacturing substrate, method of manufacturing organic electroluminescent display device using the method, and organic electroluminescent display device May 23, 2006 7148119 Process for production of semiconductor substrate Dec 12, 2006 Claims What is claimed is:

1. A method for making a thin film semi-conductor comprising the steps of:

forming a first porous layer having a first porosity on a surface of a substrate;
forming a second porous layer within or underneath said first porous layer having a second porosity higher than said first porosity;
forming at least one semi-conductor thin film on said surface; and
separating said semi-conductor film from said substrate along a line of relative weakness defined in or adjacent one of said first and second porous layers,

wherein said first porous layer and said second porous layer are formed by anodizing.

2. A thin film semi-conductor formed by:

providing a semi-conductor substrate having a surface;
forming a first porous layer having a first porosity on a surface of said substrate;
forming a second porous layer within or underneath said first porous layer having a second porosity higher than said first porosity;
forming at least one semi-conductor thin film on said surface; and
separating said semi-conductor film from said substrate along a line of relative weakness defined in or adjacent one of said first and second porous layers to obtain said thin film semi-conductor,

wherein said first porous layer and said second porous layer are formed by anodizing.

3. A thin film semi-conductor formed by:

providing a semi-conductor substrate having a surface;
anodizing said semi-conductor substrate at a first current density to provide a first porous layer adjacent said surface having a first porosity;
anodizing said semi-conductor substrate at a second current density higher than said first current density to provide a second porous layer adjacent said first porous layer opposite said surface, said second porous layer having a second porosity greater than said first porosity;
annealing said semi-conductor substrate in a hydrogen atmosphere after said step of anodizing said semi-conductor substrate to provide said second porous layer; and
forming at least one semi-conductor film on said surface.

4. A thin film semi-conductor formed by:

providing a semi-conductor substrate having a surface;
forming a first porous layer adjacent said surface having a first porosity;
forming a second porous layer within said first porous layer having a second porosity higher than said first porosity;
forming at least one semi-conductor film on said surface; and
separating said semi-conductor film from said semi-conductor substrate along a line of relative weakness defined in or adjacent one of said first and second porous layers.

Digg Newsvine Blogger The Potential of Thin-Film Crystalline Silicon Solar Cells If the efficiency and cost targets can be met, thin-film crystalline silicon solar cells have the potential to become a solid alternative to the bulk multicrystalline silicon solar cells that currently dominate the photovoltaics market. Koen Snoeckx, Guy Beaucarne, Filip Duerinckx, Ivan Gordon and Jef Poortmans, IMEC, Leuven, Belgium—Semiconductor International, 6/1/2007

The cost of silicon accounts for about half of the production cost of current industrial silicon solar cells. In order to reduce the amount of consumed silicon, the photovoltaics (PV) industry is counting on a number of options being developed in research. The most obvious one is to move to thinner silicon substrates. Presently, the thickness of silicon substrates for solar cell production is slightly above 200 µm, but technologies to cope with substrate thicknesses to slightly <100 µm are under development. To go for active silicon thickness as low as 5-20 µm, a layer of active silicon can be deposited on top of a lower-cost substrate. This approach is described by the term thin-film crystalline silicon solar cells. In order to be industrially viable, the challenge is to find the ideal trade-off between efficiency and reduced cost in a process suited for large-scale production. To manufacture the active silicon layer, several possibilities exist.1 We are investigating three such alternatives. Thin-film PV basics

The first route is to create epitaxial thin-film solar cells (Fig. 1 ) by starting with highly doped crystalline silicon wafers (e.g., from upgraded metallurgical grade silicon or scrap material), and depositing an epi layer by chemical vapor deposition (CVD). Next to the cost and availability advantages, this approach enables a gradual transition from a wafer-based to a thin-film technology. As the process is similar to a classical bulk silicon process, this technology is easier to implement in existing lines than any other thin-film technology.

Secondly, in thin-film solar cells based on layer transfer, one could deposit a monocrystalline layer epitaxially on a porous silicon film that is — at some point in the process — separated from the substrate. The idea is to reuse the parent substrate many times, so that the final wafer cost per solar cell is low. An interesting option under investigation is the possibility of processing the freestanding film by separating the porous silicon film prior to epitaxy. 1. The epitaxial thin-film silicon solar cell approach features the advantages of substrate availability and likeness to existing wafer processes.

Finally, for thin-film polysilicon solar cells, a layer of only a few microns of crystalline silicon is deposited on a cheap foreign substrate, such as a ceramic (Fig. 2 ) or high-temperature glass. Polycrystalline silicon films with grain sizes between 1-100 µm appear to be particularly good candidates. We have demonstrated that good polycrystalline silicon solar cells can be obtained using aluminum-induced crystallization of amorphous silicon. This process leads to very thin layers with an average grain size around 5 µm. These seed layers are then epitaxially thickened into absorber layers several microns in thickness using high-temperature CVD with a deposition rate exceeding 1 µm/min. Ceramic alumina and glass ceramics are used as substrates. We selected thermal CVD because of the high growth rates and achievable crystalline quality. This choice, however, imposes the use of a heat-resistant substrate material such as a ceramic. This technology is not yet as mature as the other thin-film technologies, but shows high cost-reduction potential. 2. The thin-film polycrystalline silicon solar cell approach uses a ceramic substrate for lower overall cost.

Results in thin-film PV technology have already led to solar cells with high efficiency or processing ease, leading to lower cost. Combining both aspects is something no one has succeeded in at this point. Some recent results, however, take another of the many necessary steps in the right direction. Improved epitaxial cells

For epi thin-film silicon solar cells, their moderate efficiency (around 12% for semi-industrial screen-printed cells) currently limits the attention that is paid to this cell type by the PV community. Compared with bulk silicon solar cells, similar levels of open-circuit voltage and fill factor (±77.8% for monocrystalline silicon solar cells) can be obtained. The short-circuit current (Jsc), however, is held back by the optically thin active layer (<20 µm). Light that traverses the epi layer is lost for collection in the highly doped, low-quality substrate. As a consequence, a difference in short-circuit current of 7 mA/cm² between both cell technologies is not uncommon. Bulk crystalline solar cells typically show Jsc values ~33 mA/cm², whereas epi thin-film cells average at ~26 mA/cm².

However, two separate developments at the cell level have positively changed this picture.2 By increasing the optical path length in the thin active layer, we reported screen-printed epi cells with Jsc approaching 30 mA/cm² and efficiencies of 13.8%.

3. Plasma texturing of the surface of epitaxial thin-film silicon solar cells leads to optical path-length enhancement and, therefore, to higher efficiencies. The first improvement that contributes to these results is an adaptation of the surface light scattering by fluorine-based plasma texturing (Fig. 3 ). Ideally, the textured surface of the active layer should be 100% diffusive (i.e., a Lambertian refractor). This would lead to photons moving through the active layer at an average angle of 60°, resulting in an optical path-length enhancement of two. In other words, a 20 µm layer would optically behave as if it were 40 µm thick. It was found that this complete light scattering could be achieved for a silicon removal of only 1.75 µm. The plasma texture brings a lot of advantages at the cell level: a lower reflection (down to 10% starting from 35% before texturing), oblique light coupling and a lower contact resistance (caused by the larger contact area between the silicon substrate and silver electrodes). An absolute improvement of 1.0-1.5 in Jsc is observed, together with an efficiency increase of 0.5-1.0%.

A second improvement was achieved by incorporating a porous silicon Bragg reflector for internal light trapping. To decrease the transmittance of long wavelength light into the substrate, an intermediate reflector was positioned at the interface between the substrate and epi layer. Photons reaching this interface can now be reflected and pass a second time through the active layer. Because the light is diffused from the moment it enters the cell (due to the Lambertian nature of the plasma texture), a large percentage of the photons will strike the front surface outside the escape angle. Therefore, most of the photons will be reflected internally for a third pass. The story repeats itself from that moment on so that multiple passes through the epi layer become possible (Fig. 1 ).

4. TEM of a reorganized porous silicon stack that serves as an embedded reflector for internal light trapping in epi thin-film solar cells. In practice, the reflector is made by electrochemical growth of a porous silicon stack of alternating layers with high and low porosity (a multiple Bragg reflector). During the epi growth of the active layer, the porous silicon stack automatically transforms into alternating layers consisting of small and large voids (Fig. 4 ). This structure has been proven to be ideal for the concept of a reflector based on constructive interference. For a 15-layer porous silicon stack, calculations lead to an optical path-length enhancement of 14. In other words, a 15 µm layer would optically behave as a 210-µm-thick silicon slab.

To validate both approaches, epi cells were processed on three different carrier substrates with cell surfaces of 18 cm². On monocrystalline silicon, serving as proof-of-concept, cell efficiencies increased up to 13.8%, with a fill factor of 77.8%, indicating that there is no conductance problem through the reorganized porous silicon stack. On low-quality silicon substrates, the results are slightly lower, with efficiencies up to 13.5% and a fill factor of 77.7%. The lower performance can be explained by the fact that the epi growth is of lower quality in the case of porous silicon on multicrystalline substrates. The optimization of this process is ongoing, and will most likely lead to higher efficiency gains in the near future. Improvement in poly thin films

For another type of solar cells, namely polycrystalline thin-film solar cells based on aluminum-induced crystallization, we recently obtained a record efficiency of 7% for this type of cell. The cells were made on high-temperature substrates using seed layers based on aluminum-induced crystallization of amorphous silicon that were epitaxially thickened into absorber layers at 1130°C. It is important to note that this process does not make use of remelting of silicon. Remelting silicon on the ceramic substrate is an alternative approach to obtain polycrystalline solar cells. However, because of the extremely high temperatures that are needed for this approach (over 1400°C), it requires substrates with outstanding thermal stability and yields a high risk for contamination. The secret behind the achievement was a dedicated design and implementation of the cell contacts combined with plasma texturing of the surface.

5. A dedicated interdigitated contact design results in better electrical characteristics of polycrystalline thin-film solar cells. Since most high-temperature substrates suited for polycrystalline silicon solar cells are insulators, new metal contact schemes have to be developed, avoiding the use of back contacts. In view of low-cost manufacturing of modules, the most convenient approach would be to integrate the cell interconnection process with the cell fabrication. Our approach uses a monolithic module process in which the cell interconnection is combined with the cell contacting. All contacts are made on top of the cells in an interdigitated pattern (Fig. 5 ). Different process sequences can be used to achieve the novel contact structure. Presently, a simple two-step laboratory process is used, combining photolithography with metal evaporation. In view of mass production, the metallization should be performed in a single step by either screenprinting or evaporation through a shadow mask.

The dedicated contact design was implemented at the cell level on cells with an active area of 1 cm² and compared with cells that had base contacts at the periphery (Fig. 6 ). The open circuit voltages (Voc) were comparable for both types, but the interdigitated cells scored remarkably better in terms of short-circuit densities (Jsc) and fill factors. Depending on the grain size and thickness of the layers, efficiencies up to 5.6% were obtained.3 6. Polycrystalline silicon solar cells with contacts at the periphery (left) and a dedicated interdigitated contact design (right) leads to higher efficiencies. (Note: Layers are not drawn to scale.)

To further enhance the current density and, hence, the efficiency of the cells, we applied an innovative cell concept using plasma texturing. So far, polycrystalline silicon solar cells were made in substrate configuration with the substrate acting as a back reflector. Texturing the front side of the cells generates more effective light trapping by lowering the front reflectivity of the cells and obtaining better coupling of light into the cell. Plasma texturing was done in a reactor using a fluorine-based chemistry. As a result, the current density was increased by ~15% (results obtained for an alumina substrate). This increase in current density boosted the cell efficiency toward the record of 7.0%.4

However, while the obtained Voc (506 mV) and fill factor (71%) can be called state-of-the-art, current densities (19.7 mA/cm²) and cell efficiencies are still too low for commercialization. By optimizing the plasma texturing process and lowering the thickness of the back surface field layer of the cells, we expect to reach efficiencies well above 7.0% in the near future. Conclusion

While the cell efficiencies of bulk crystalline solar cells are still in another league (up to 18% on 130 µm thin cells recently reported), the substantially lower cost potential of thin-film cells justifies the continuous and increasing research effort of the international PV community. By 2010, thin-film crystalline silicon solar cells on non-silicon substrates are predicted to reach a fabrication cost below 1 euro per Watt peak. Which fabrication route will finally lead to a manufacturable process is hard to predict at this stage. All have their pros and cons. For epi thin-film silicon solar cells, the most recent results are promising and encouraging, but efficiencies in the range of 14-15% should be attained before considering mass production. In addition, scale up of the equipment for growing epi layers, as well as the manufacturing of low-cost silicon substrates, are requisites for successful introduction into the industry. Also for polycrystalline thin-film solar cells, envisaged efficiencies over 7% are going in the direction of what is needed for commercialization, certainly because of the very low cost of the substrate. Major obstacles to overtake remain the optimization of the production processes and their conversion toward more standard solar-cell production steps. Acknowledgements

This work was partially funded by the European research programs Athlet, Meteor and Latecs, as well as the FP5 and FP6 programs Epimetsi, Sweet and Crystal Clear. Author Information Koen Snoeckx is a scientific editor for IMEC . E-mail: Koen.Snoeckx@imec.be Guy Beaucarne is the group leader of solar cell technology. Filip Duerinckx is a senior scientist in the solar cell technology group. Ivan Gordon is a scientist in the solar cell technology group. Jef Poortmans is the program director of Solar+ at IMEC.

References

1. J. Poortmans et al., “Thin-Film Crystalline Si Solar Cells: Facts and Challenges,” Tech. Dig. 14th Intl. Photovoltaic Sci. Engin. Conf. (PVSEC-14), 2004, p.13.
2. F. Duerinckx et al., “Optical Path-Length Enhancement for >13% Screenprinted Thin Film Silicon Solar Cells,” 21st Euro. Photovoltaic Solar Energy Conf. and Exh., September 2006.
3. I. Gordon et al., “Development of Interdigitated Solar Cell and Module Processes for Polycrystalline-Silicon Thin Films,” Thin Solid Films, 2006, Vol. 511-512, p. 608.
4. I. Gordon et al., “Thin-Film Polycrystalline-Silicon Solar Cells on High-Temperature Substrates by Aluminium-Induced Crystallization,” 21st Euro. Photovoltaic Solar Energy Conf. and Exh, September 2006.

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Listen To: Solar Cell Production: Mono vs. Poly Crystalline Podcast Peter Woditsch, CEO of Deutsche Solar AG (Freiberg, Germany), talks about the company’s solar cell manufacturing operations.

US Patent Issued on November 9, 2004

Inventor(s) Fabrice Letertre Thibaut Maurice

Assignee S.O.I.TEC Silicon on Insulator Technologies S.A. Application No. 327790 filed on 2002-12-23

Current US Class 438/406 , Bonding of plural semiconductive substrates 438/409 , Porous semiconductor formation 438/455 , BONDING OF PLURAL SEMICONDUCTOR SUBSTRATES 438/456 , Having enclosed cavity 438/457 , Warping of semiconductor substrate 438/458 , Subsequent separation into plural bodies (e.g., delaminating, dicing, etc.) 438/479 , On insulating substrate or layer 438/690 , Combined with the removal of material by nonchemical means (e.g., ablating, abrading, etc.) 438/735 , Differential etching of semiconductor substrate 438/964 ROUGHENED SURFACE

Field of Search 438/406 , Bonding of plural semiconductive substrates 438/409 , Porous semiconductor formation 438/455 , BONDING OF PLURAL SEMICONDUCTOR SUBSTRATES 438/456 , Having enclosed cavity 438/457 , Warping of semiconductor substrate 438/458 , Subsequent separation into plural bodies (e.g., delaminating, dicing, etc.) 438/479 , On insulating substrate or layer 438/690 , Combined with the removal of material by nonchemical means (e.g., ablating, abrading, etc.) 438/735 , Differential etching of semiconductor substrate 438/753 , Silicon 438/964 ROUGHENED SURFACE

Examiners Primary: Matthew Smith Assistant: Victor Yevsikov

Attorney, Agent or Firm Winston & Strawn LLP

US Patent References 5395788 Method of producing semiconductor substrate Issued on: March 7, 1995 Inventor: Abe, et al. 5539245 Semiconductor substrate having a gettering layer Issued on: July 23, 1996 Inventor: Imura, et al. 6010579 Reusable substrate for thin film separation Issued on: January 4, 2000 Inventor: Henley, et al. 6326279 Process for producing semiconductor article Issued on: December 4, 2001 Inventor: Kakizaki, et al.

Foreign Patent References 199 43 101 DE. Apr., 2001 62 179110 JP Jan., 1988 02 194519 JP Oct., 1990

Abstract Claims Description Full Text

Description

CROSS REFERENCE TO RELATED PATENT APPLICATION

This application claims the benefit of French National Patent Application No. 0116713, filed Dec. 21, 2001, which is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates in general to the fabrication of semiconductor substrates, and more particularly, to assembling a donor wafer.

BACKGROUND

Known techniques for preparing a wafer that includes a thin semiconductor layer for forming circuitry (e.g., electronic, optoelectronic, or optical circuits or components) include Smart-Cut.RTM. type processes. In general, such processes involve implantation of a gaseous species at a controlled depth in a bulk donor wafer in order to create a weakness at a desired depth in the donor wafer, and the application of stresses to cause a separation at the desired depth due to the weakness. Molecular adhesion or wafer bonding may have been used before separation to bond a receiving wafer with a layer of the bulk donor wafer to be separated. Molecular adhesion or wafer bonding may be typical techniques by which the separated layer from the donor wafer and the receiving wafer are assembled. Once separated, further processing for producing circuits or components for the circuits in the separated layer may take place.

In some circumstances (e.g., when re-use is desired), it may be desired to subject the remaining structure of the donor wafer to further processing. The remaining structure may be the subject of mechanical, chemical-mechanical, or other polishing steps to ready remaining portions of the donating material of the donor wafer for further use. Other processing activities may involve chemical cleaning steps, relatively high temperature operations (e.g., 300 to 900° C., such as for oxide deposition), or substantially high temperature operations (e.g., 1150° C., such as for thermal oxidation in cases such as a silicon carbide wafer).

In some circumstances, it may be desired to recycle the bulk donor wafer through reuse. In such circumstances, the remaining structure may be required to be subject to additional implantation of one or more gaseous species, bonding with a receiving wafer, or further separation steps (e.g., through thermal or mechanical stresses).

Such reuse may progressively decrease the thickness of the donor wafer through consecutive removal of thin layers from the donor wafer. Progressively decreasing the thickness of the donor wafer may lead to an excessively thin donor wafer, which may not be reusable for further recycling.

There are other difficulties or deficiencies that are faced in recycling a donor wafer. There may be a high risk of fracture during predominantly mechanical operations such as when stress is applied to separate a thin layer from the donor wafer or such as when bonding is performed through CMP planarization of a surface oxide, etc. A high risk of fracture also arises for example during high-temperature heat treatment. The risk may be due to non-uniform temperatures in a donor wafer.

There may also be a high risk of fracture when an operator or processing machinery is required to handle a donor wafer. Another deficiency may involve large strains that are induced in certain operating steps when a donor wafer has been thinned through reuse. Operations such as implanting gaseous species or certain deposition steps may induce strains in thinner donor wafers that may cause the wafers to sag significantly (e.g., causing a wafer to take on a convex profile). Sagging may seriously compromise operations that require suitably flat contacting surfaces. Thus, a donor wafer may not be usable for further recycling once a minimum donor wafer thickness has been reached (e.g., a thickness at which deficiencies or drawbacks mentioned above may exist).

Discontinuing recycling at a minimum donor wafer thickness may be economically detrimental and/or inefficient in material consumption because the remaining material is typically discarded as waste material. Deficiency in this process is heightened in cases where the semiconductor material of a donor wafer is relatively expensive (e.g., is a high quality semiconductor material) or relatively fragile. For example, in the case of a standard silicon carbide wafer (e.g., a silicon carbide wafer having a standard diameter of 2 inches), a wafer thinned to about 200 µm may become unusable either because of frequent fractures during the process or because of a sag caused by implantation of gases prevents the wafer from suitably bonding to a receiving wafer.

In other applications, thickness may be relatively thin from a starting donor wafer (e.g., because wafers for a particular semiconductor material are typically offered on the market at that thickness). Gallium Nitride donor wafer may be one such example. Known techniques for producing such wafers involve using a thick eptixay technique called HPVE (Hybrid Vapour Phase Epitaxy) on an epitaxially grown substrate (seed layer) that is removed after epitaxy. This technique, however, has two major drawbacks. Firstly, it only makes it possible to obtain self-supporting wafers having a thickness of at most around 200 to 300 µm. If a greater thickness is sought, imperfect lattice matching with the seed layer may generate excessive strains. Secondly, the rate of growth using the thick epitaxy technique is extremely slow (typically, 10 to 100 µm per hour). Such drawbacks may seriously handicap manufacturing costs.

Drawbacks may also be associated with conventional techniques in which ingots of some single crystal semiconductor material such as SiC are used for producing bulk donor wafers. In conventional techniques in which ingots of semiconductor material such as SiC are used for producing bulk donor wafers, the following operating steps are typically implemented: the ingot may be cut (e.g., using a saw) into slices having a thickness of around 1 mm, each of the faces of the slice may be coarsely polished to remove crystal damaged by sawing and to obtain good planarity, and the future front face (the removal face) may be successively polished to obtain appropriate surface roughness. Such techniques, which may start from relatively thick slices, may often involve substantial losses of material during the successive polishing steps. This obviously affects the manufacturing cost.

Thus, there is a need for providing such processes and structures in a more economically advantageous and efficient way. Within this context, there may also be a need to continue recycling even when extremely small thickness is reached.

BRIEF SUMMARY OF THE INVENTION

In accordance with the principles of the present invention, a process for repeated treatment of wafers may provided that involves preparing a reusable donor wafer for donating a thin layer of semiconductor material by assembling a donor layer of semiconductor material (e.g., a monocrystalline semiconductor material) having a thickness of plural thin layers onto a support layer (e.g., a support layer of a non-monocrystalline semiconductor material). Thus, a support layer is provided in a donor wafer that is of a lower quality or less precious than the donor layer of the wafer. With respect to “less precious,” for example, monocrystalline silicon may be considered to be less precious than monocrystalline silicon carbide or another example may be that monocrystalline material of one semiconductor may be considered to be less precious than a higher quality monocrystalline material of the same semiconductor due to differences (e.g., substantial differences) in price, availability, or usability. Such processes may be for providing an electronic, opotoelectronic, or optical component.

In one aspect, a process may be provided for transferring successive thin layers from a semiconductor material of a donor wafer to a receiving wafer. A bulk slice may be assembled that includes a donor layer of a semiconductor material and a support layer. The donor layer and the support layer may form a mechanically stable assembly, which may constitute a donor wafer. A region of weakness may be created in the donor layer at a controlled depth. The donor wafer may be bonded to a receiving wafer via the free side of the donor layer of the donor wafer. A separation may be effected in the region of weakness of the donor layer to transfer a thin layer of the semiconductor material from the donor wafer to the receiving wafer. The process may be repeated to recycle the “assembled” donor wafer without breaching the support layer of the donor wafer.

If desired, assembly of the donor wafer may be carried out by wafer bonding using polished faces of the donor layer (which may be a bulk slice) and a support (which may be the support layer). High temperature welding between polished faces may also be used for preparing the assembly. If desired, a region of weakness may be created by implanting gaseous species. In some embodiments, wafer bonding may be implemented to bond the donor wafer to the receiving wafer. Separation of the thin layer may be effected by applying stresses, especially thermal and/or mechanical stresses.

With the use of a support layer, the donor wafer may be recycled a maximum number of times to separate thin layers from the donor layer. The maximum number of times may depend on the thickness of the donor layer and the depth at which a weakness is created in the donor wafer in each cycle.

If desired, the donor layer may be a single crystal semiconductor material and the support may be a single crystal of inferior quality, a single crystal material of a different semiconductor, the same semiconductor in polycrystalline form, or the same semiconductor as a different polytype. The semiconductor material of the donor layer, support layer, or both may for example be silicon, silicon carbide, or large-gap monometallic or polymetallic nitrides. In some embodiments, the donor layer may for example have a thickness of around 100 to 300 µm. In some embodiments, the support layer may for example have a thickness of around 100 to 300 µm.

The semiconductor material of the donor layer, support layer, or both may be a large-gap monometallic or polymetallic nitride such as gallium nitride.

If desired, the support layer may be a bulk layer and may be produced for example from silicon, gallium nitride, silicon carbide, aluminum nitride, or sapphire.

Another aspect is aimed at producing donor wafers with reduced losses, and therefore with more profitable use of the starting material (in this case single-crystal SiC). A process may be provided for producing a donor wafer intended to be used in a process for transferring successive thin layers of a given semiconductor material from the donor wafer to a receiving wafer. The process may involve producing a bulk slice of the semiconductor material and assembling the bulk slice and a support in order to form the donor wafer. These techniques may alleviate some of the drawbacks in conventional technology that exists when a slice from an ingot of a semiconductor material (e.g., SiC) is used as a bulk donor wafer.

If desired, the bulk slice may be produced by sawing an ingot or by thick-film epitaxy on a seed layer. If thick film epitaxy is used, the step of removing the seed layer may be implemented.

The bulk slice may be polished only on its face that is intended to come into contact with the support. In the prior art, both faces are typically coarsely polished. Polishing may be performed to a defined degree on the face of the bulk slice and the face of the support which are intended to come into contact with each other.

Assembling the bulk slice and the support may be carried out at a temperature and for a time such that wafer bonding or welding may be achieved between the bulk slice and the support. The semiconductor material of the bulk slice may be a single-crystal semiconductor and the support may be chosen from the group comprising the same semiconductor as the bulk slice but with a single crystal of inferior quality, the same semiconductor in polycrystalline form, or the same semiconductor as a different polytype. The bulk slice, the support, or both may be silicon, silicon carbide, or large-gap monometallic or polymetallic nitrides (e.g., gallium nitride). If desired, the support layer, the bulk slice, or both may be produced from silicon, gallium nitride, silicon carbide, aluminum nitride, or sapphire. If desired, other materials may be contemplated.

Further features, objects and advantages of the present invention will become more clearly apparent on reading the following detailed description of preferred embodiments of implementation of the invention, the description being given by way of non-limiting example and with reference to the appended drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1a-1e are block diagrams of semiconductor materials in an illustrative sequence for preparing a reusable donor wafer and forming a thin layer from the donor wafer for forming electronic, optoelectronic, and optical circuitry in accordance with embodiments of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Techniques may be provided in which the cost and inefficiency in existing recycling techniques involved in Smart-Cut.RTM. type processes may be addressed. By bonding a support layer with a donor layer, an inexpensive handle wafer for the donor semiconductor material may be provided. Costs may be reduced by employing a support layer of a less-expensive semiconductor material since the primary purpose of the support layer will be to provide mechanical support for the donor layer during processing treatment that may involve, for example, implantation of gaseous species, bonding the donor side of a donor-support assembly to a receiving wafer, separating a thin layer from the donor-support assembly, polishing after separation, and/or other further processing treatments. Lesser amounts of donor semiconductor materials may be scrapped using such techniques since a portion of the minimum thickness that is required for such processing may be fulfilled using the support layer. Bonding techniques may be implemented in such processes to use a donor layer and support layer that are made different types of semiconductor material.

In some embodiments, a starting donor wafer, that is used in a process for removing successive thin layers, may be formed by assembling a donor slice and a mechanical support. The assembling operation may be implemented using for example wafer bonding, performed on the donor slice and/or on the mechanical support and using appropriate interface bonding layers when appropriate.

A mechanical support may be chosen to have characteristics that are compatible, especially in terms of temperatures, with processing operations that will be applied to the donor wafer in successive cycles of removing thin layers from the donor slice. In this respect, one important factor may be the relationship between the thermal expansion coefficient of the material of the donor slice and that of the material of the mechanical support. Firstly, “homo-assemblies” may be distinguished, that is to say those with materials for the donor layer and for the support layer that have similar chemical and mechanical properties. Examples of such assemblies may include:

single-crystal SiC (donor) on low-quality single-crystal or polycrystalline SiC (support);

single-crystal GaN (donor) on low-quality single-crystal or polycrystalline GaN (support); and

single-crystal Si (donor) on low-quality single-crystal or polycrystalline Si (support).

When “homo-assemblies” are used, there is practically no limitation with respect to a thermal budget for producing the donor wafer. In such circumstances, the two materials are thermally well matched and the donor layer will typically be undisturbed by diffusion or the like.

“Hetero-assemblies”, as opposed to “homo-assemblies” may be considered to be assemblies in which materials for the donor layer and for the support layer have different mechanical and/or chemical properties. Examples of “hetero-assemblies” may include single-crystal SiC (donner) on Si (support), indium phosphide InP on Si, and GaN on Si. Other “hetero-assemblies” may also be implemented.

In “hetero-assembly” type cases, the thermal budget or the temperature to which the assembly may be exposed may be more limited because there may exist a thermal mismatch between components of the assembly. A thermal mismatch may result in deformation or fracture. For example, in the case of a donor wafer made of SiC (donor layer) on Si (support layer), difficulties arise with temperatures of around 900 to 950° C. being exceeded.

Another factor to be considered is the thickness of the donor slice/support assembly produced, which may be selected to be compatible with the steps of the treatment that the wafer is to undergo and selected to allow as much of the donor layer to be consumed.

Once the bonding has been carried out and if necessary strengthened by suitable treatments, this assembly may be considered a full-fledged donor wafer, which may be handled during the successive process operations of removing thin layers as if it were a conventional bulk donor wafer that is homogeneous throughout its thickness. The number of thin layers removed may be chosen essentially according to the thickness of the donor layer and the depth of the region of weakness so that the final removal is effected without the support layer being reached and without any regions of defects likely to exist at the transition between the donor layer and the support layer, being reached.

If necessary, when the assembling operation has been completed, the donor wafer may be thinned at its rear face (on the support layer side) in order to adjust the thickness of the wafer and make it compatible with downstream technological steps and with possible standards. For example, when the support layer is made of silicon, this thinning step can be very easily carried out by mechanical lapping.

EXAMPLE 1

SiC case

When a donor slice consists of single-crystal SiC, it may be assembled on a support that comprises polycrystalline SiC. The assembling operation may be carried out by direct bonding or else by producing, on the faces to be assembled, intermediate layers made of silicon oxide SiO2 for example.

Bonding may be performed by facilitating a bonding surface of the donor layer, support layer or both to suitably bond with the donor layer and support layer. For example, in cases where the donor is layer is monocrystalline and the support is polycrystalline, an amorphous layer may be formed on the support to facilitate the bonding of the two layers. Examples of such techniques are illustratively shown in Attorney Docket No. 4717-5100 entitled “Method of Fabricating Substrates and Substrates Obtained by This Method” which was filed on Dec. 16, 2002, and which is incorporated herein in its entirety.

In terms of polarity, a SiC single crystal is, for example, bonded to a support on its Si face, whereas the C face of the single crystal is the exposed face from which thin layers will subsequently be removed. The reverse situation may also be possible. The question of polarity may occur with all materials having a hexagonal crystal structure such as GaN and AlN.

An initial polishing step on this face as well as intermediate polishing steps between two successive removal operations may preferably be carried out.

Because of the fact that the single-crystal SiC of the donor slice and the polycrystalline SiC of the mechanical support both have expansion coefficients close to 4.5×10-6 /K, the assembly thus formed may undergo, without any damage, all the recycling, chemical cleaning, deposition and heat treatment steps associated with the Smart-Cut process for transferring thin layers.

According to a variant, the mechanical support may be made of silicon. In this case, compatibility between the support and the donor slice from the thermal standpoint may prove to be inferior, but nevertheless remains satisfactory in particular if the maximum temperatures to which the assembly is subjected during the treatments are limited. For example it may be limited, by producing the oxide layers involved in bonding the thin layer using deposition and not thermal oxidation.

Advantageously, the fabrication of the donor slice/mechanical support assembly in this example may for example involve: cutting a slice from an ingot with a thickness substantially less than the usual thickness that is conventionally used for bulk single-crystal SiC donor wafers (e.g., a thickness of around 500 µm rather than around 1 mm); performing a polishing operation that is carried out on only one of the faces of the slice; positioning the polished face in intimate contact with a face of a suitably planar polycrystalline SiC support wafer to bond them together by wafer bonding; and producing the support wafer having a thickness for example of around 200 to 300 µm (before bonding with the donor layer) typically by thick-film deposition of the CVD type. It should be noted that a low-quality (and therefore inexpensive) single-crystal SiC, or a SiC of a polytype different from that of the donor layer (for example, 6H SiC for the support and 4H SiC for the donor layer), could also be used for the support.

Additional processing steps may include, exposing the assembly to a suitable thermal budget (for example 1100° C. for 2 hours) in order to obtain suitable bonding forces between the slice and the support wafer. The degree of polishing of the contacting faces should also be taken into account so that satisfactory wafer bonding may be obtained under the aforementioned conditions. A single thick single-crystal SiC (donor layer)/polycrystalline SiC (mechanical support layer) combination wafer may thus be obtained. As a variant, it may also be possible simply to lay the wafers on top of one another and bond them together by welding (typically at temperatures of 2000° C. or higher); however, this is more demanding.

The combination wafer is then polished on the free face of the single-crystal SiC, with the standard degree of polishing, in order to end up with a single-crystal SiC layer having no buried work-hardened region and having a suitable surface roughness.

This process may thus produce donor wafers with much less loss of expensive material (e.g., single-crystal SiC) than the technique mentioned in the introduction of using bulk slices. Moreover, the donor layer and the support may be assembled upstream in-the wafer fabrication line, and therefore may not effect the process of transferring layers from the donor wafer to a receiver wafer.

The potential savings that may be achieved are even greater when the particular SiC ingot of interest is more difficult and/or more expensive to produce (e.g., a semi-insulating SiC ingot of very high purity obtained by HTCVD or of an SiC ingot having a very low concentration of intrinsic crystal defects such as dislocations and micropipes).

EXAMPLE 2

The GaN case

In the case of the use of Smart-Cut.RTM. type techniques with a GaN donor wafer, various steps employed may involve temperatures that are generally very much lower than those encountered in the case of SiC. Thus, the problem of the respective thermal expansion coefficients of the support and the donor wafer is less crucial. This may give more flexibility in the choice of support material.

In the present example, a GaN slice of a thickness for example of around 100 to 200 µm may be wafer bonded to a mechanical support made of polycrystalline or single-crystal SiC for example. As in the case of SiC, the polarity of that face of the GaN wafer which will be on the support side and, consequently, the reverse polarity of that face of the wafer on the free side, that is to say on the side from which layers are removed, may be determined in advance.

The support layer/GaN donor layer assembly becomes a fully-fledged wafer used until the donor layer has been completely or almost completely consumed in the various cycles of a Smart-Cut.RTM. process.

Techniques described herein are illustratively shown in sequences shown in FIGS. 1a to 1e.

Slice 10 may be the semiconductor material that will form successively transferred thin layers. Wafer 20 may be a support wafer.

In FIG. 1b, slice 10 and support wafer 20 may be assembled using techniques illustratively described herein or using other techniques to form donor wafer 30. In FIG. 1c, buried region of weakness 12 may be formed at a certain depth from the free surface of donor layer 10. Region 12 may define thin layer 101 with respect to remainder 102 of the donor layer. In FIG. 1d, wafer bonding may be carried out between the free face of donor layer 10 (if necessary, with prior oxidation or other treatment on this face) and one face of receiving wafer 40 (if necessary, also with prior oxidation or other treatment on this face).

In FIG. 1e, a separation is performed, especially by thermal and/or mechanical stress, at the region of weakness 12 in order to obtain, on the one hand, desired assembly 40, 101, typically forming a substrate for applications in electronics, optoelectronics or optics, and, on the other hand, donor wafer 30’ whose donor layer 10, essentially corresponding to region 102, has been substantially thinned down by the thickness of thin layer 101 that has been transferred.

These steps may be repeated with donor wafer 30’ until donor layer 10 has been almost entirely consumed, without however breaching support layer 20.

In one implementation, steps shown in FIGS. 1a and 1b may be carried out on the premises of the donor wafer fabricator, whereas the following steps may be part of a separate process carried out on the premises of the fabricator of composite substrates for electronics, optoelectronics and optics industries.

Of course, the invention applies to the production of wafers comprising donor layers made of other materials, such as aluminum nitride and more generally semiconductor, especially large-gap, monometallic or polymetallic nitrides, diamond, etc., or else single-crystal silicon of very high quality for the donor layer and low-quality single-crystal or polycrystalline silicon for the support.

It is to be understood that the invention is not to be limited to the exact configuration as illustrated and described herein. Accordingly, all expedient modifications readily attainable by one of ordinary skill in the art from the disclosure set forth herein, or by routine experimentation there from, are deemed to be within the spirit and scope of the invention as defined by the appended claims.

• * * * *

Thin Solid Films Volumes 403-404, 1 February 2002, Pages 34-38 Proceedings of Symposium P on Thin Film Materials for Photovoltaics

ect Porous silicon as a substrate for hydroxyapatite growth Vacuum Vacuum, Volume 76, Issues 2-3, 5 November 2004, Pages 135-138 L. Pramatarova, E. Pecheva, D. Dimova-Malinovska, R. Pramatarova, U. Bismayer, T. Petrov and N. Minkovski

Porous silicon as a substrate for hydroxyapatite growth

Abstract Porous silicon has been shown to be an excellent candidate biomaterial, following studies establishing its biostability and non-toxicity. These favorable properties, coupled with the ease of its topographical manipulation, make it a promising material for the growth of hydroxyapatite, which is used as an artificial bone material. In this paper, the use of porous silicon as a substrate for hydroxyapatite growth induced by two methods is reported: a simple soaking process in a simulated body fluid and a laser–liquid–solid interaction process which allows interaction between a scanning laser beam and the substrate immersed in the simulated body fluid. The grown layers are investigated by light microscopy, electron microprobe analysis and X-ray diffraction. It is found that the layer topography obtained after applying the two processes is different. Abstract | Full Text + Links | PDF (323 K) Epitaxial silicon growth on porous silicon by reduced p… Materials Science and Engineering B Materials Science and Engineering B, Volume 4, Issues 1-4, October 1989, Pages 435-439 C. Oules, A. Halimaoui, J. L. Regolini, R. Herino, A. Perio, D. Bensahel and G. Bomchil

Epitaxial silicon growth on porous silicon by reduced pressure, low temperature chemical vapour deposition

Abstract Epitaxial growth of silicon on porous silicon layers has been obtained at a low temperature (820°C) in a reduced pressure vapour phase apitaxy reactor, using SiH4 as the reactive gas and a lamp-heating system allowing rapid thermal processing. Silicon epitaxy has been studied on different porous layers formed on both highly doped (p+, n+) and lightly doped (p, n) substrates. As shown by cross-sectional transmission electron microscopy observations, very good crystalline quality is obtained for epitaxial layers growm over p+- and n+-type porous layers, with the same defect density as that obtained in epilayers grown in the same conditions on bulk silicon. However, the initial porosity of the layer appears to be a critical parameter, and a defect density increase is observed if the porosity of the substrates exceeds 50%. In the case of lightly doped substrates, although single-crystal growth is actually obtained, a large defect density is found. Abstract | Abstract + References | PDF (449 K) The origin of visible luminescencefrom “porous silicon”... Solid State Communications Solid State Communications, Volume 81, Issue 4, January 1992, Pages 307-312 M. S. Brandt, H. D. Fuchs, M. Stutzmann, J. Weber and M. Cardona

The origin of visible luminescencefrom “porous silicon”: A new interpretation

Abstract Luminescence and vibrational properties (infrared and Raman) of anodically oxidized (“porous”) silicon and of chemically synthesized siloxene (Si6O3H6) and its derivates are compared. Based on the quantitative agreement of these two types of materials it is concluded that the origin of the strong room temperature luminescence in “porous” silicon can be traced to siloxene derivates present in “porous” silicon. Abstract | Abstract + References | PDF (415 K) Structure and morphological studies of thin porous sili… Vacuum Vacuum, Volume 58, Issues 2-3, August 2000, Pages 351-357 P. Vitanov, M. Delibasheva, E. Goranova, Ch. Angelov and V. Dimov

Structure and morphological studies of thin porous silicon layers

Abstract Porous silicon (PS) thin films of thicknesses between 50 and 120 nm were formed by electrochemical etching in HF : C2H5OH : H2O solution. The porous films prepared on n- and p-type Si wafers were characterized by scanning electron microscopy (SEM), atomic force microscopy (AFM) and transmission electron microscopy (TEM). The thin porous layers have crystalline silicon skeleton with columnar pores extended perpendicular to the films surface. Abstract | Full Text + Links | PDF (658 K) Elastic reflection of electrons by porous silicon layer… Applied Surface Science Applied Surface Science, Volume 115, Issue 2, 1 June 1997, Pages 111-115 C. Robert, L. Bideux, B. Gruzza, E. Vazsonyi and G. Gergely

Elastic reflection of electrons by porous silicon layered (PSL) surfaces: effects of porosity

Abstract The electrical and optical properties of porous silicon layers deposited on silicon substrates are determined by their electrochemical preparation conditions. Porous silicon layers (PSL) deposited on low resistivity (10−3 ω cm) boron doped p+ Si exhibits channel structure, whereas layers formed on p type (1–3 ω cm) Si wafers are sponge type. In the abundant literature on PSL, little attention was paid to their electron spectra. We presented in this paper, a study of p+ and p type PSL samples by elastic peak electron spectroscopy (EPES). The elastic reflection coefficient re(E, P) is strongly affected by physical parameters of the sample as the porosity, the substrate Si type as well the presence of H adatoms within the pores. re(E, P) spectra are measured in absolute units (%) with a retarding field analyzer. A general tendency of spectra was the decrease of intensity with P (porosity) and E (primary electron energy). We have observed that HF treatment of the samples is producing a dramatic decrease of reH(E, P) in the low energy range (E = 50–150 eV). reH(E, P) intensities were measured at E = 50, 100 and 150 eV. We observed that the excess reflection (coming from the pores sides) becomes important for porosity P > 0.6. A phenomenological model is presented based on the intact Si surface and reflection of electrons from the pores. Abstract | Abstract + References | PDF (366 K)

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doi:10.1016/S0040-6090(01)01554-1 Copyright © 2002 Elsevier Science B.V. All rights reserved. Transfer of a thin silicon film on to a ceramic substrate

C. S. Solanki, , a, R. R. Bilyalova, J. Poortmansa and J. Nijsa, b a IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium b Katholieke Universiteit Leuven, Electrotechnical Department, Leuven, Belgium

Available online 25 January 2002.

Abstract In a scenario of large volume photovoltaic production, the cost of the Si starting substrate is almost 70% of the total module level cost. In such cases thin film crystalline silicon technology has large potential to reduce the cost of solar cells if a method to combine a high-quality Si film with a low-cost substrate is found. A process of transferring a thin porous silicon layer (PSL) onto a ceramic substrate like alumina is described. Separation of PSL from its parent Si substrate is obtained either by double porosity layer formation followed by high temperature annealing at 1050°C in H2 or by carrying out electrochemical etching for a sufficiently long time at constant formation parameters. The transfer of PSL to alumina substrate is carried out using spin-on oxide or pyrolytic oxide as an intermediate layer. The quality of the transfer is checked by means of a scratch test. Reflectance characteristics of PSL transferred onto alumina substrate reveal an effective light passing.

Author Keywords: Thin film; Porous silicon; Ceramic substrate; Layer transfer

Porous silicon layer transfer processes for solar cells

C. S. Solanki, , R. R. Bilyalov, J. Poortmans, J. Nijs† and R. Mertens‡ IMEC vzw, Kapeldreef 75, 3001, Leuven, Belgium

Available online 9 April 2004.

Abstract A promising cost-effective way of converting sun light into electricity could be a solar cell realized in a thin monocrystalline silicon film, due to its potential to achieve cell efficiencies of more than 20% in a 20 μm thick film. A porous silicon layer transfer technique provides an opportunity to get monocrystalline films on low-cost substrates such as glass. This paper reviews various processes, which are being developed for the layer transfer using porous silicon as a sacrificial layer while reusing of starting silicon substrate. The four basic steps—porous silicon formation, active layer deposition, layer separation and transfer, and device fabrication—have been identified in layer transfer process. The processes have been categorized and compared on the basis of the sequence of steps used in individual processes.

Original Paper New Approach for the Formation and Separation of a Thin Porous Silicon Layer C.S. Solanki, R.R. Bilyalov, H. Bender, J. Poortmans Interuniversity Micro-Electronics Center (IMEC) vzw, Kapeldreef 75, B-3001 Leuven, Belgium

email: C.S. Solanki (chetans@imec.be)

Abstract A new one-step method is developed for the formation and separation of a thin porous silicon film (PSF) by electrochemical etching of silicon in hydrofluoric (HF) acid based solution. This provides advantages over the existing techniques, which are requiring multiple-steps for fabrication and separation of a thin layer from the substrate. The in-situ change in the fluoride ion concentration results in the formation of a high porosity layer beneath the low porosity layer under the same formation condition, which is confirmed by detailed morphological analysis. In-situ separation of a thin porous silicon film from the substrate is obtained by carrying out an anodization for sufficiently long time. A two-step approach is also proposed which consists of an electrochemical etching followed by an electrochemical polishing step and provides a better control over the separation condition than the one-step approach.

Nanosolar Ships First Panels December 18, 2007 Posted by Martin Roscheisen, CEO

After five years of product development – including aggressively pipelined science, research and development, manufacturing process development, product testing, manufacturing engineering and tool development, and factory construction – we now have shipped first product and received our first check of product revenue.

We are grateful to everyone who supported us through all these years and the many occasions where there appeared to be mile-high concrete walls in our path; the unusual intensity and creativity of our team deserves all the credit for achieving this major milestone today.

Our product is defining in more ways I can enumerate here but includes:

- the world’s first printed thin-film solar cell in a commercial panel product;

- the world’s first thin-film solar cell with a low-cost back-contact capability;

- the world’s lowest-cost solar panel – which we believe will make us the first solar manufacturer capable of profitably selling solar panels at as little as $.99/Watt;

- the world’s highest-current thin-film solar panel – delivering five times the current of any other thin-film panel on the market today and thus simplifying system deployment;

- an intensely systems-optimized product with the lowest balance-of-system cost of any thin-film panel – due to innovations in design we have included.

Today we are announcing that we have begun shipping panels for freefield deployment in Eastern Germany and that the first Megawatt of our panels will go into a power plant installation there.

As far as the first three of our commercial panels are concerned:

Panel #1 will remain at Nanosolar for exhibit.

Panel #2 can be purchased by you in an auction on eBay starting today.

Panel #3 has been donated to the Tech Museum in San Jose.

[These are obviously not the first three we ever produced – we have produced loads for testing – but these are the first three of what we consider our commercial panels.]

Related Info: Nanosolar Shipping for Megawatt Municipal Power Plant

Main Index

Copyright © 2002 – 2008, Nanosolar, Inc. All rights reserved.

FormFactor Introduces Harmony Wafer-Level Burn-In Probe Card Posted by EDA Geek News Staff in Test Solution on Thursday, October 18, 2007 ST Unveils Cartesio STA2062 Automotive Processor with Embedded GPS » « DS2 Creates 400Mbps Powerline Technology FormFactor, Inc. (Nasdaq:FORM) announced the introduction of the latest addition to its Harmony™ family of full-area, 300-mm wafer probe solutions—the Harmony Wafer-Level Burn-In (WLBI) probe card. The Harmony WLBI probe card is designed to maximize throughput, as well as ensure higher quality and reliability of semiconductor devices. The Harmony WLBI probe card sets a milestone with the ability to contact approximately 40,000 test pads in one touchdown, enabling the testing of an entire 300-mm wafer at high temperature (up to 130 degrees Celsius). This capability helps IC manufacturers meet their reliability and performance requirements at the lowest cost of test.

FormFactor has shipped Harmony one-touchdown WLBI probe cards to multiple customers for reliability testing of leading-edge DRAM devices. With FormFactor’s Harmony WLBI cards, throughput can be increased by as much as an order of magnitude, to help reduce time-to-market.

The Harmony WLBI probe card incorporates advanced electronics and a new 3-D MEMS MicroSpring® contactor, designed to withstand the rigors of high-temperature burn-in testing and minimize cleaning—further increasing probe card availability and test cell productivity. FormFactor’s proprietary technology can also amplify the number of die simultaneously tested with existing tester resources, allowing manufacturers to better leverage their depreciated test equipment.

Harmony WLBI is an important component in FormFactor’s suite of probe card solutions for enabling known good die (KGD) applications, where devices must be tested to specification before packaging. Examples of KGD applications include mobile cell phones and portable media players, where multiple device types are incorporated into a single system-in-package (SiP) or multi-chip package (MCP).

“The consumer market is extremely time-sensitive, with very short design cycles. Each day of delay in time-to-market can mean millions of dollars to manufacturers,” stated Ofer Bokobza, vice president and general manager of FormFactor’s DRAM Product Business Group. “Our Harmony WLBI probe card solution offers maximum throughput, which is critical to help our customers reduce their time-to-market. At the same time, the efficiency of one-touchdown burn-in allows our customers to migrate more reliability testing to the wafer-level, an important step forward in enabling KGD.”

FormFactor is now taking Harmony WLBI probe card orders.

About FormFactor Founded in 1993, FormFactor, Inc. (Nasdaq: FORM) is the leader in advanced wafer probe cards, which are used by semiconductor manufacturers to electrically test ICs. The company’s wafer sort, burn-in and device performance testing products move IC testing upstream from post-packaging to the wafer level, enabling semiconductor manufacturers to lower their overall production costs, improve yields, and bring next-generation devices to market. FormFactor is headquartered in Livermore, California with operations in Europe, Asia and North America.

FormFactor, Harmony WLBI, Harmony and MicroSpring are trademarks or registered trademarks of FormFactor, Inc.

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1. Double-sided anodization 2. Donor silicon layer is etched in a cross pattern, channels formed filled with glass (CTE > Si) but can withstand epi temperatures, epi grown on exposed siliocn not covered by glass, after growth of epi si, the donor wit epi is cooled to RT, the lateal stresses generated by the differential cte of glass and siliocn will cause teh fracrure of silicon. In fact, the donor wafer need not be etched, but the glass may be screen printed and fired on the silicon. After firing, the silicon oxide on areas not coverd by glass is etched off briefly with HF. 3. Create isalnds of low expansion glass on the substrate, grow epi-silicon, upon cooling from the epi temperature the CTE mismatch between the epi siliocn and glass mounds, will exert a peeling force on the former, causing it peel. This process can be helped if there was foremd a porous silicon layer adjacent to the the glass mounds.

Separation process for silicon-on-insulator wafer fabrication Document Type and Number:United States Patent 6387829 Link to this page:http://www.freepatentsonline.com/6387829.html Abstract:A process for manufacturing a silicon-on-insulator wafer from a silicon wafer assembly. The assembly is made of two wafers. One of the wafers contains a fragile layer. The fragile layer is a layer containing a high amount of hydrogen. An amount of energy from an energy source is applied to the assembly to separate the assembly along the fragile layer thus forming a silicon-on-insulator wafer and a leftover wafer. The energy source is selected from the group consisting of: ultrasound, infrared, hydrostatic pressure, hydrodynamic pressure, or mechanical energy. The amount of energy is chosen to be sufficient to transform the fragile layer into a quasi-continuous gaseous layer. Under separation the hydrogen-enriched layer transforms into layer consisting of hydrogen platelets and hydrogen microbubbles.

Solar & Alternative Energy

New solar cell production process may improve efficiency and reduce cost

Mustapha Lemiti, Anne Kaminski, Alain Fave and Erwann Fourmond

Solar cells can be made better and less expensively by creating them on a sacrificial silicon layer and then transferring them to a low-cost substrate. Photovoltaics is a renewable energy that can reduce pollution and climate change effects. A serious alternative to fossil energy, the solar industry is showing exponential growth in production. Currently about 90% of fabricated solar modules are made of crystalline silicon. Materials costs represent about 45% of the total module price. One way to make the photovoltaic industry more competitive is to reduce the consumption of silicon and increase the efficiency of solar cells.

Approaches to trimming materials costs include replacing crystalline silicon with silicon thin films deposited on cheap substrates at low temperatures. However, the efficiency of solar cells made using this technique is limited by the low quality of the material. Cutting thinner wafers of crystalline silicon from the ingot can also decrease costs, but mechanical problems limit this method. We are developing silicon thin films that are epitaxially grown on a sacrificial layer and transferred to a cheap foreign substrate.1 To maximize the potential of this material, we combine it with rear contact solar cell technology.

Figure 1 illustrates the process we use to create these solar cells. First, we create a sacrificial porous silicon layer on top of a monocrystalline silicon substrate. A high-quality single-crystal silicon film is then grown by epitaxy on this surface. The rear contact solar cell is created on this film. All metallic contacts are deposited on the rear side of the cell to avoid shadowing effects and to allow high efficiencies. A low-cost substrate (glass or ceramic) is then stuck on the back side of the cell. Using the sacrificial layer, the cell is separated from the initial wafer, which can be recycled several times.2

Figure 1. Process to create solar cells with lower cost and higher efficiency.

Figure 2. Scanning electron microscope (SEM) image of the beginning of the separation between the initial substrate and epitaxial layer via the high porosity silicon layer. The porous sacrificial layer, made by the electrochemical anodization of silicon, actually contains two layers: one with low porosity to facilitate growth of a high-quality epitaxial layer and one with high porosity to permit separation at the end of the process (see Figure 2). The epitaxy of the 50µm-thick silicon layer is performed by either liquid or vapor phase epitaxy (1µm/min). The usual growth temperature is 1000° C, but we are also studying the possibility of low-temperature liquid-phase epitaxy (<900° C).

At first we optimized the rear contact solar cell by 2D simulation and manufactured it using photolithography. To simplify this process, we developed a new self-aligning process (see Figure 3) based on anisotropic etching of silicon after metallization of the emitter. During creation of the solar cell, the front surface is carefully passivated by silicon nitride. We have optimized the stoichiometry of the silicon nitride to obtain the best compromise between the passivation and antireflection properties of the layer. We are also studying the possibility of enhancing the efficiency of the solar cell using the luminescence effect of silicon nanocrystals embedded in the silicon nitride layer. Finally, the solar cell is attached to a cheap substrate and separated mechanically from its original silicon substrate. This can be reused in a new cycle. The process has been tested several times on the same initial substrate.

The main limitations on photovoltaic energy development are material cost and efficiency. We can overcome these problems by creating high-efficiency solar cells on epitaxially grown single-crystal silicon on a sacrificial porous silicon layer. We have demonstrated the feasibility of this process on 2in. wafers and are now transferring it to 4in. wafers. This will permit the process to be studied on large-area solar cells and potentially to be transferred to industry.

Figure 3. Left: Self-aligned rear contact solar cell (the illuminated face is on the bottom of the figure). Right: SEM view of back contacts.

Mustapha Lemiti, Anne Kaminski, Alain Fave and Erwann Fourmond Laboratoire de Physique de la Matière, National Institute of Applied Sciences, Lyon (INSA-Lyon) Villeurbanne, France Mustapha Lemiti is a professor at the Laboratoire de Physique de la Matière. His group’s research focuses mainly on the production and characterization of crystalline silicon solar cells.

Anne Kaminski is an assistant professor at INSA-Lyon. She specializes in solar cell design, technology, and characterization.

Alain Fave is an assistant professor at INSA-Lyon. He is involved in silicon epitaxy and solar cell technology.

Erwann Fourmond is an assistant professor at INSA-Lyon. He works on plasma deposition systems as well as solar cell technology and characterization.

References: 1. J. Kraiem, S. Amtablian, O. Nichiporuk, P. Papet, J. F. Lelièvre, A. Fave, A. Kaminski, M. Lemiti, ELIT: epitaxial layer for interdigitated back contacts on transferred solar cells, 21st EPSEC, pp. 1268-1271, Dresden, Germany, 2006. 2. J. Kraiem, O. Nichiporuk, P. Papet, A. Fave, A. Kaminski, E. Fourmond, J.-P. Boyeaux, P.-J. Ribeyron, A. Laugier, M. Lemiti, Interdigitated back contacts solar cells on transferred Si thin film epitaxially grown on porous silicon, PVSEC-15, pp. 746-747, Shanghai, China, 2005. DOI: 10.1117/2.1200702.0572

1/29/08 9;20 PM Listening to bob dyalan on PBS. Got this idea: Coat pyrex glass with molynd ni Immersion gold Plate layer of tin Melt and dissolve silicon, heat to supersaturate Cool to precipitate si If excess silicon seeds exist, they will continue to grow Can try this today Ravi sent – Exploratory research for advanced photovoltaix by Howrd Branz of NREL—-4/2007

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Flexible Solar Cells: OEM Components

The OEM Components line consists of the most basic of flexible solar cell technology. There are 22 different cells in three different product lines to choose from, ranging in size, voltage, current, and encapsulation material. Each cell is created by depositing amorphous silicon on a thin plastic substrate and then encapsulating the cells in either a Polyester coating or heavy duty Tefzel, a DuPont product. The cells are paper thin and can be wrapped around almost any curved surface. The three product lines are the Electronic Series, the RC Aircraft Series, and the WeatherProTM Series. Each series has been designed with certain characteristics. The Electronics Series is perfect for integration into small portable electronics. The RC Aircraft Series has the best weight to power ratio as they were constructed with model aircraft in mind. The WeatherProTM Series was built for permanent fixture in the outdoors, as the Tefzel coating has a rated lifespan of 20 years. Barrier Coatings and Stability of Thin Film Solar Cells

3rd Quarterly Report – Phase I: March 1, 2005 — May 31, 2005

NREL Subcontract: 48027

1. OBJECTIVES/APPROACH

The key objectives of the program are to develop low cost barrier coatings for CIS and CdTe solar cells and to develop an improved understanding of the effects of water on the stability of these types of cells. The scope of this work entails investigations of multilayer, barrier coatings for CIS and CdTe thin film solar cells, and studies of stability issues, particularly those related to moisture ingress.  Investigation of barrier coatings on SSI and CSU devices will continue in an effort to establish effective approaches to encapsulate CIS and CdTe modules.  Studies will also be directed towards issues concerning cost of the coating process.  The program will be structured into three major tasks:  (1) Barrier coatings and stability studies for CIS Solar Cells; (2) Barrier coatings and stability studies for CdTe solar cells; (3) Low cost coating process development.

2. PROGRESS FOR THIS REPORTING PERIOD

Work concentrated on studies concerning encapsulation of CdTe cells.  Three topics are discussed: further consideration of results for a CSU cell encapsulated with a single dyad/Al-film combination; results for studies of stressed bare cell cells from CSU and University of Toledo; and studies of encapsulated calcium samples subjected to heat and humidity conditions.

2.1 Results for CSU Cell Encapsulated with One Dyad and Al Film

Results for stress tests for a CSU cell encapsulated with a single dyad and an aluminum film were discussed in the last quarterly report.  Very positive results were obtained for the cell stressed for 1000 hours under 60ºC/90%RH conditions.  After being stressed for 1000 hours, we decided to change the stress conditions to 85C/85%RH to further characterize the ability of this relatively simple approach to encapsulation.  Results for I-V parameters are shown in Figure 1.   The main effect of the 60/90 stress

Figure 1. I-V parameters for CSU cell encapsulated by a single dyad combined with aluminum film subjected to 60ºC/90%RH followed by 85ºC/85%RH. was an increase in Rs which caused a decrease in FF. The effects of 85/85 stress are more extensive. In particular, all parameters degraded as a result of the 85/85 stress. Part of the cell degradation may simply be due to thermal effects. Dry heat studies at 85ºC will be carried out next quarter so that we can identify thermal effects separately. Another key point to be determined is the effect of lateral migration of moisture. All encapsulation procedures used to date have not incorporated an edge seal. Studies discussed below show that lack of an edge seal could be affecting our results.

2.2 Studies with Bare CSU Cells

Efficiency results for bare CSU cells subjected to 60C/90%RH are given in Figure 2.  The cell areas are 0.3 cm2.  Cells were enclosed in an environmental chamber under dark and open circuit conditions.  These results represent a very significant improvement relative to efficiency data reported for bare CSU cells in 2004.  CSU indicated that the carbon/nickel material used to form a back contact is greatly improved over that used in 2004.   These results compare very favorably to those reported below for bare Toledo cells.

Figure 2. Efficiency vs time for bare CSU cells in environment of 60ºC/90%RH.

2.3 Studies with Bare UT Cells

Encapsulation studies of University of Toledo cells were initiated last quarter.  The effort began with examining the effects of moisture on bare devices.  The UT cells utilize a superstrate configuration and are approximately one cm2 in area.   Data were taken at three conditions, dry heat at 60ºC, 60ºC/90%RH and 85ºC/85%RH.    These results suggest that moisture moves through the front contact structure rather slowly.  However, encapsulation is clearly required to achieve a stable cell.  Future studies will involve application of transparent multilayer encapsulation.

Figure 3. Efficiency vs time for bare UT cells in three different environments, dry conditions at 60ºC, 60ºC/90%RH and 85ºC/85%RH.

2.4 Investigation of Moisture Ingress with Encapsulated Calcium Layers

Studies were carried out with encapsulated calcium films in an effort to understand the pathways taken by moisture in the encapsulated cell structures.  Samples described by Figure 4 were used for the study.  A 500 Å thick calcium film was deposited onto glass and then transferred to the coating system where it was stored in nitrogen prior to encapsulation.  The encapsulated  samples were then subjected to various environmental conditions involving stress due to temperature and moisture.  Moisture interaction with the calcium films results in the formation of Ca(OH)2, which is transparent.  The multi-layers of polymer and Al2O3 utilized for encapsulation are transparent to the visible

Figure 4. Sample structure for testing dynamics moisture ingress.

spectrum. Thus, whereas the coated calcium films are not transparent at the beginning of the various tests, moisture ingress results in formation of transparent regions of Ca(OH)2 in the sample allowing one to observe where moisture ingress occurs.

Figures 5 and 6  show results for samples with one dyad and five dyad coatings after being subjected to 60ºC/90%RH, 85ºC /50%RH and 85ºC /85%RH for 120 hours.   For each type of coating three samples were subjected to 60ºC/90%RH, two samples to 85ºC /50%RH and one sample to 85ºC /85%RH.   In case of the single dyad coating, moisture penetrates through the interior of the encapsulation as well as from the edges.  In fact for an environment of 85ºC /85%RH, the calcium film has been converted completely to Ca(OH)2 in the case the sample with only one dyad coating.  The results are much different for the calcium films encapsulated with five dyad coatings.   After 120 hours, there is no indication of moisture ingress for any of the stress conditions.

Figures 7 and 8 give results for the encapsulated calcium samples after 550 hours.  The calcium samples with only one dyad coating are completely converted to Ca(OH)2 in the case of two of the three samples subjected to 60ºC/90%RH and for the sample subjected to 85ºC/85%RH.  The samples stressed at 85/50 are nearly completely converted also.  It is interesting that the 60/90 condition appears to have a larger effect than 85/50.  It should also be noted that results for 85/50 stress indicate that although moisture penetrates the interior region, diffusion of water from the edges is a very significant cause of water ingress.   The results for the samples with five dyad coatings are very instructive.  They clearly establish that with five dyads, the dominant mechanism for moisture ingress is due to diffusion from the edges.  It seems clear that edge seals will be a subject we must address in future studies.   The results for 60/90 stress described in Figure 8 are quite impressive, and, in fact, consistent with results of life tests carried out with encapsulated CSU CdTe cells and SSI CIGSS mini-modules.

Figure 5. Samples with one dyad encapsulation (See Figure 4) that were subjected to 60ºC/90%RH, 85ºC/50%RH and 85ºC/85%RH for 120 hours.

Figure 6. Samples with five dyad encapsulation (See Figure 4) that were subjected to 60ºC/90%RH, 85ºC/50%RH and 85ºC/85%RH for 120 hours.

Figure 7. Samples with one dyad encapsulation (See Figure 4) that were subjected to 60ºC/90%RH, 85ºC/50%RH and 85ºC/85%RH for 550 hours.

Magnetic edge seal for solar collector film Document Type and Number: United States Patent 4419982 Link to this page: http://www.freepatentsonline.com/4419982.html Abstract: An edge seal for a solar collector type flexible film material is provided for forming a generally air-tight heat insulating reusable seal around the edge of an opening in the surface of a building structure. The edge seal is formed around the film material which is sized to cover the window opening and overlap the edges of the opening. A band of magnetically permeable particles is adhered along the edge of the substrate forming the film material by a suitable adhesive. A strip of magnetic material is adhered around the edge of the opening. The permeable particles are attracted to the magnetic strip to form an effective air-tight seal between the flexible film material and the opening to essentially form a dead air space between the flexible material and the window opening. The flexible film material can be mounted similar to a window shade adjacent to the upper edge of the opening. The film material can also have a monolayer of transparent spheres adhered to one side which provide a means for concentrating solar energy striking the outer surface of the sheet material. The solar energy will be converted to heat energy and conducted through the sheet material to the interior surface so that the heat will be transferred to the interior of the building. Inventors: Eckels, Robert E. (2101 Youngfield, Golden, CO, 80401) Application Number: 06/376297 Filing Date: 05/10/1982 Publication Date: 12/13/1983

What I claim is:

1. A magnetic edge seal for a flexible solar collector film material for forming a generally air-tight, heat insulating, reusable seal around the edges of a window opening in a surface of a building, the magnetic edge seal being provided to trap the air adjacent to said window opening to prevent it from entering the interior of said building while permitting solar energy to be converted to heat energy by said flexible film material so as to heat the air within said building, the magnetic edge seal comprising: (a) a flexible film sheet material sized to overlap the edges of said window opening, said film material having a monolayer of transparent spheres adhered to the surface of said material facing said window opening; (b) said flexible film material being arranged to be stored in the retracted position by being wrapped around a rotatably mounted roller positioned adjacent to the upper edge of said window opening; (c) said rotatably mounted roller being positioned within an enclosed cover means positioned along the upper edge of said window opening whereby said edge is essentially sealed to prevent air flow; (d) said film material being arranged to be extended downwardly across the said window opening by unrolling from said rotatably mounted roller whereby the sheet material completely covers said window opening and overlaps the edges of said opening; (e) the edges of said sheet material having a continuous band of magnetically permeable particles adhered thereto; and (f) a continuous magnetic strip means applied along the edges of said window opening corresponding to the overlapping edges of said sheet material containing said magnetically permeable particles, said magnetically permeable particles being attracted to said magnetic strip means whereby an effective air-tight seal is provided around the outer edges of said film material whereby the air adjacent to the window opening is essentially enclosed and trapped to prevent movement to the interior of said building while allowing the solar energy collected on the surface of said flexible material to be converted to heat energy and conducted to the interior of said building. Description: FIELD OF THE INVENTION This invention is directed to an edge seal and a method of producing an edge seal for a solar collector type of flexible film which covers a structure opening. It is more specifically directed to a magnetic type of edge seal for a window shade having a monolayer of optical spheres adhered to a flexible substrate used for covering a window opening. BACKGROUND OF THE INVENTION In the past I have described various ways for producing a flexible solar collector material which has a plurality of glass spheres adhered to one surface of the substrate. In U.S. Pat. No. 4,033,324 which issued on July 5, 1977, I described an arrangement for mounting a plurality of focusing elements on a solar energy absorbing substrate. The elements focus solar energy rays into a series of hot spots focused on the surface of the substrate which provides a high temperature for transfer of the heat energy to the opposite side of the substrate material. In U.S. Pat. No. 4,054,125 I describe an arrangement whereby a dark colored absorbing substrate covered with the monolayer of the transparent spheres is provided for absorbing solar radiation for heating an air column formed between the substrate and the inside of a transparent window. In one form of this invention a drapery material forms with the substrate a series of tubes for naturally or forcibly circulating warm air through the tubes when the substrate is heated by solar radiation. Reflecting cover material, selectively mountable in front of the monolayer substrate, reflects solar radiation back through the transparent window when heating is not required. My presently pending patent application Ser. No. 224,630 describes a unique method for forming a stable, monolayer of transparent spheres on a sheet-like substrate by flowing a stream of spheres in a cascading arrangement over the sloped surface of the substrate material coated with a suitable adhesive. The spheres which adhere to the substrate material, are then set by either applying light pressure or the application of a thin film of clear transparent material. This provides a novel substrate material having a fairly complete cover of uniform sized glass spheres adhered to one side of the surface of the material to form the solar concentrating function. When the material which is formed by this method is utilized in the fabrication of window covers or shades, it performs a very useful function. When in the drawn position, the solar energy which impinges on the outer surface of the shade heats the inside surface of the substrate film which in turn heats the air next to the film causing the heated air to rise by convection. In addition, heat energy is also radiated into the room directly by the heated interior surface of the substrate film. In this way, solar energy is transformed into heat energy which is utilized for heating the interior of a room or other enclosed area. In the use of this material, it has been found that a considerable increase in the efficiency of the device can be obtained by sealing the edge of the shade along all edges of the window in order to trap the cold air next to the window forming an insulating factor and preventing the cold air from escaping into the interior of the room. With this arrangement the seal becomes very effective during the night time hours. As can be expected, there are many difficulties in attempting to seal the edges of a window shade of this type. One of these is the necessity to be able to raise and lower the shade at will. In order to do this, it is necessary to be able to quickly and easily release the bottom and side edges of the window shade as desired when it is necessary to raise or lower the shade. It is also necessary that the seal for this type of device be easily released or attached so that by merely raising and lowering the shade and putting it in place the seal can be made or broken. In the past it has been attempted to use a slotted channel on each side of the shade to hold and retain the edges of the shade in close proximity to the window frame to form a quasi air-tight seal. As can be readily expected if the channel is very narrow, it is difficult to move the shade. With this hindrance, it makes it difficult to use the shade with the final result that the shade is either pulled from the channels or the sides are cut or torn rendering any seal useless. In addition, the bottom of the shade is seldom properly retained, or if it is it is by use of a mechanical seal or lock which usually is very cumbersome and difficult to use. The present invention solves all of these problems by rendering a very quick and easy seal which is completely or is substantially air-tight when in place. When combined with a solar collector type device, unique and gratifying results are obtained with the applicant’s invention. PRIOR ART STATEMENT The following is a brief discussion of the most pertinent patents of which the inventor is aware. This is not intended as a complete discussion of these patents and reference should be made to the patents themselves for a determination of their disclosure. The Angelita patent (U.S. Pat. No. 3,960,135) discloses a combination window solar heater and thermal barrier. This patent discloses a vertically-oriented, highly heat absorbant surface within a box which has been mounted within the frame of a window. The construction of the box provides a flexible gasket seal around the outside edges of the window frame to seal the air space within and control the movement of air flow through the box by convection heating. Pivotally mounted doors are provided on the interior surface of the box to allow the heated air within that box to flow to the interior of the adjacent room. The patent to Robert A. Mole (U.S. Pat. No. 4,020,826) shows another window solar energy system in which a radiant energy absorbing drapery is mounted adjacent to the interior surface of a window. This drapery can be reversed so as to reflect the solar energy, if desired. The drapery is mounted with a space between the drapery and the window sash to allow air circulation to be provided by convection heating. The Restle, et al. patent (U.S. Pat. No. 3,990,635) describes a solar collector for a window opening which includes two transparent substrate film sheets stored on rollers such as a window shade. The edges of this film material move in slots provided on each side of the window sash to provide a seal along both sides of the film. Since this slot can not have a close tolerance, it is obvious that air flow around the edges of the film can occur. SUMMARY OF THE INVENTION This invention is directed to a solar energy absorbing system for use with an opening provided in the exterior surface of a structure. The solar collector sheet material forming the basis for the system includes a flexible substrate film having a monolayer of transparent beads adhered along one surface. The collector material is arranged to be mounted on a retractable roller provided at the upper edge of the window opening. The collector material which is utilized in the fabrication of this device utilizes a multitude of glass or plastic spheres which are adhered to the surface of the substrate film and arranged so that solar energy striking the spheres will be concentrated optically onto the surface of the substrate. The conversion of the solar energy takes place in the substrate where the solar energy is changed to heat energy and this heat is transferred to the interior surface of the film by conduction. Since considerable heat energy is lost through or around a window or building opening, it is desirable to seal the edges of the collector material around the space adjacent to the window. In this way, a dead air cavity can be provided between the window and the substrate film so that the air is trapped between these elements to produce an insulator to reduce actual heat loss from the room. In order to accomplish this arrangement in a simple and low cost structure the collector film material can be mounted and operated in a manner similar to a window shade. This shade arrangement is attached along one edge to a wood or metallic roller which is supported at each end by suitable brackets. By grasping the edge of the film material, it can be pulled down across the window opening as it is unrolled from the roller. In this way, the film can be positioned over the window opening or wound back onto the roller to expose the window as desired. During manufacture of the collector material, the surface of the film is coated with a suitable adhesive and the film is mounted on a support surface in a generally vertical position. A quantity of transparent glass or plastic spheres of suitable size and optical quality is cascaded over the surface of the film starting at the uppermost edge. The application of the glass spheres can be performed either manually or by machine as desired during this portion of the manufacturing process. It is desirable that these spheres shall not be embedded more than one-third of their height in the adhesive coating. It has been found that this depth can be controlled by carefully adjusting the angle of the surface with the vertical plane. In accordance with the present invention, prior to the application of the glass spheres to the adhesive, a cover strip is applied around the outside edges of the film sheet so as to cover the adhesive in this area. With the cover strip applied, the glass spheres are prevented from adhering to the protected edge areas. After the transparent spheres have been applied, the protecting strips are removed and a granular or powdered magnetically permeable or attractable material is applied to the exposed adhesive area. The particle size can be from as little as 10 microns to particles as large as 1/16th of an inch or more in average diameter. It is desirable, however, that the approximate size of the particles be similar to the optical units or transparent spheres which are adhered to the surface of the substrate film. This is helpful in order to maintain a balance between the energy absorbing surface and the edges to prevent difficulty in the winding of the material when used as a window shade. These particles are fabricated from iron or other suitable ferrous materials which are attracted to magnets and other magnetic devices. The applied magnetically permeable particles are set into the adhesive by applying a light force with a soft roller. It is also possible that a clear plastic or other type of coating can be applied to the particles to seal their surface. This sealing coat may be necessary where there is a considerable amount of moisture in the ambient atmosphere to prevent the iron or ferrous particles from oxidizing and forming a rust byproduct. In order to form the other half of the seal a plurality of short strips of magnetic material is adhered to the edge of the window frame along both sides. In the alternative a continuous strip of magnetic material can be applied along both edges of the window frame. The width of the substrate material which forms the solar collector shade is arranged to overlap the edge of the window frame and the magnetic strip material which is applied thereto. In this way when the collector material is drawn down across the window opening and positioned adjacent to the frame, the iron particles will be attracted to the magnetic strips forming a generally tight seal which prevents air flow around the edges of the material. As an additional embodiment of the present invention, when a steel casement window is encountered, it is possible that the edge strip along the material can be formed from small magnetic particles which are embedded in the adhesive. In this way the magnetic particles can be attracted directly to the iron or steel material in the edge of the window sash or frame forming a seal between the film material and the window structure directly. It is also within the scope of this invention that the iron or magnetically permeable particles can be embedded along the end of the film adjacent to the bottom of the window opening. In the same way the magnetic strip material can be adhered along the bottom edge of the window op